[AW-CCS]am335x-evm.dts 20 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "am33xx.dtsi"
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. / {
  12. model = "TI AM335x EVM";
  13. compatible = "ti,am335x-evm", "ti,am33xx";
  14. chosen {
  15. stdout-path = &uart0;
  16. tick-timer = &timer2;
  17. };
  18. cpus {
  19. cpu@0 {
  20. cpu0-supply = <&dcdc2_reg>;
  21. };
  22. };
  23. memory {
  24. device_type = "memory";
  25. //reg = <0x80000000 0x10000000>; /* 256 MB */
  26. reg = <0x80000000 0x20000000>; /* 512 MB */ /* +++ vern,512MB DDR ,20181030 ---*/
  27. };
  28. vbat: fixedregulator@0 {
  29. compatible = "regulator-fixed";
  30. regulator-name = "vbat";
  31. regulator-min-microvolt = <5000000>;
  32. regulator-max-microvolt = <5000000>;
  33. regulator-boot-on;
  34. };
  35. lis3_reg: fixedregulator@1 {
  36. compatible = "regulator-fixed";
  37. regulator-name = "lis3_reg";
  38. regulator-boot-on;
  39. };
  40. wlan_en_reg: fixedregulator@2 {
  41. compatible = "regulator-fixed";
  42. regulator-name = "wlan-en-regulator";
  43. regulator-min-microvolt = <1800000>;
  44. regulator-max-microvolt = <1800000>;
  45. /* WLAN_EN GPIO for this board - Bank1, pin16 */
  46. gpio = <&gpio1 16 0>;
  47. /* WLAN card specific delay */
  48. startup-delay-us = <70000>;
  49. enable-active-high;
  50. };
  51. matrix_keypad: matrix_keypad@0 {
  52. compatible = "gpio-matrix-keypad";
  53. debounce-delay-ms = <5>;
  54. col-scan-delay-us = <2>;
  55. row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
  56. &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
  57. &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
  58. col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
  59. &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
  60. linux,keymap = <0x0000008b /* MENU */
  61. 0x0100009e /* BACK */
  62. 0x02000069 /* LEFT */
  63. 0x0001006a /* RIGHT */
  64. 0x0101001c /* ENTER */
  65. 0x0201006c>; /* DOWN */
  66. };
  67. gpio_keys: volume_keys@0 {
  68. compatible = "gpio-keys";
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. autorepeat;
  72. switch@9 {
  73. label = "volume-up";
  74. linux,code = <115>;
  75. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  76. gpio-key,wakeup;
  77. };
  78. switch@10 {
  79. label = "volume-down";
  80. linux,code = <114>;
  81. gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  82. gpio-key,wakeup;
  83. };
  84. };
  85. backlight {
  86. compatible = "pwm-backlight";
  87. pwms = <&ecap0 0 50000 0>;
  88. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  89. default-brightness-level = <8>;
  90. };
  91. panel {
  92. compatible = "ti,tilcdc,panel";
  93. status = "okay";
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&lcd_pins_s0>;
  96. panel-info {
  97. ac-bias = <255>;
  98. ac-bias-intrpt = <0>;
  99. dma-burst-sz = <16>;
  100. bpp = <32>;
  101. fdd = <0x80>;
  102. sync-edge = <0>;
  103. sync-ctrl = <1>;
  104. raster-order = <0>;
  105. fifo-th = <0>;
  106. };
  107. display-timings {
  108. 800x480p62 {
  109. clock-frequency = <30000000>;
  110. hactive = <800>;
  111. vactive = <480>;
  112. hfront-porch = <39>;
  113. hback-porch = <39>;
  114. hsync-len = <47>;
  115. vback-porch = <29>;
  116. vfront-porch = <13>;
  117. vsync-len = <2>;
  118. hsync-active = <1>;
  119. vsync-active = <1>;
  120. };
  121. };
  122. };
  123. sound {
  124. compatible = "ti,da830-evm-audio";
  125. ti,model = "AM335x-EVM";
  126. ti,audio-codec = <&tlv320aic3106>;
  127. ti,mcasp-controller = <&mcasp1>;
  128. ti,codec-clock-rate = <12000000>;
  129. ti,audio-routing =
  130. "Headphone Jack", "HPLOUT",
  131. "Headphone Jack", "HPROUT",
  132. "LINE1L", "Line In",
  133. "LINE1R", "Line In";
  134. };
  135. };
  136. &am33xx_pinmux {
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
  139. matrix_keypad_s0: matrix_keypad_s0 {
  140. pinctrl-single,pins = <
  141. 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
  142. 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
  143. 0x60 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */
  144. 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
  145. 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
  146. 0x6c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
  147. >;
  148. };
  149. volume_keys_s0: volume_keys_s0 {
  150. pinctrl-single,pins = <
  151. 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
  152. 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
  153. >;
  154. };
  155. i2c0_pins: pinmux_i2c0_pins {
  156. pinctrl-single,pins = <
  157. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  158. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  159. >;
  160. };
  161. i2c1_pins: pinmux_i2c1_pins {
  162. pinctrl-single,pins = <
  163. 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  164. 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  165. >;
  166. };
  167. uart0_pins: pinmux_uart0_pins {
  168. pinctrl-single,pins = <
  169. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  170. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  171. >;
  172. };
  173. uart1_pins: pinmux_uart1_pins {
  174. pinctrl-single,pins = <
  175. 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
  176. 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
  177. 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
  178. 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
  179. >;
  180. };
  181. clkout2_pin: pinmux_clkout2_pin {
  182. pinctrl-single,pins = <
  183. 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  184. >;
  185. };
  186. nandflash_pins_s0: nandflash_pins_s0 {
  187. pinctrl-single,pins = <
  188. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  189. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  190. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  191. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  192. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  193. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  194. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  195. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  196. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  197. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  198. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  199. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  200. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  201. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  202. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  203. >;
  204. };
  205. ecap0_pins: backlight_pins {
  206. pinctrl-single,pins = <
  207. 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  208. >;
  209. };
  210. cpsw_default: cpsw_default {
  211. pinctrl-single,pins = <
  212. /* Slave 1 */
  213. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* MII1_RX_ER.gmii1_rxerr */
  214. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
  215. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_txclk.mii1_txclk */
  216. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
  217. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd3.rgmii1_rd3 */
  218. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd2.rgmii1_rd2 */
  219. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd1.rgmii1_rd1 */
  220. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd0.rgmii1_rd0 */
  221. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
  222. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.rgmii1_td3 */
  223. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.rgmii1_td2 */
  224. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.rgmii1_td1 */
  225. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
  226. >;
  227. };
  228. cpsw_sleep: cpsw_sleep {
  229. pinctrl-single,pins = <
  230. /* Slave 1 reset value */
  231. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_RX_ER.gmii1_rxerr */
  232. //0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_COL.gmii1_col */
  233. //0x10C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_CRS.gmii1_crs */
  234. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  235. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  236. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  237. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  238. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  239. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  240. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  241. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  242. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  243. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  244. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  245. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  246. >;
  247. };
  248. davinci_mdio_default: davinci_mdio_default {
  249. pinctrl-single,pins = <
  250. /* MDIO */
  251. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  252. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  253. >;
  254. };
  255. davinci_mdio_sleep: davinci_mdio_sleep {
  256. pinctrl-single,pins = <
  257. /* MDIO reset value */
  258. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  259. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  260. >;
  261. };
  262. #if 0
  263. mmc1_pins: pinmux_mmc1_pins {
  264. pinctrl-single,pins = <
  265. 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  266. >;
  267. };
  268. #endif
  269. mmc1_pins_default: pinmux_mmc1_pins {
  270. pinctrl-single,pins = <
  271. 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  272. 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  273. 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  274. 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  275. 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  276. 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  277. /*0x0A8 (PIN_INPUT | MUX_MODE7)*/ /* LCD_DATA2.GPIO2_8 */
  278. 0x08C (PIN_INPUT | MUX_MODE7) /* GPMC_CLK.GPIO2_1 */
  279. >;
  280. };
  281. mmc3_pins: pinmux_mmc3_pins {
  282. pinctrl-single,pins = <
  283. 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
  284. 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
  285. 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
  286. 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
  287. 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
  288. 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
  289. >;
  290. };
  291. wlan_pins: pinmux_wlan_pins {
  292. pinctrl-single,pins = <
  293. 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
  294. 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
  295. 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
  296. >;
  297. };
  298. lcd_pins_s0: lcd_pins_s0 {
  299. pinctrl-single,pins = <
  300. 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
  301. 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
  302. 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
  303. 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
  304. 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
  305. 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
  306. 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
  307. 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
  308. 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  309. 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  310. 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  311. 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  312. 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  313. 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  314. 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  315. 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  316. 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  317. 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  318. 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  319. 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  320. 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  321. 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  322. 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  323. 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  324. 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  325. 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  326. 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  327. 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  328. >;
  329. };
  330. #if 0
  331. am335x_evm_audio_pins: am335x_evm_audio_pins {
  332. pinctrl-single,pins = <
  333. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
  334. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
  335. 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
  336. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
  337. >;
  338. };
  339. #endif
  340. dcan1_pins_default: dcan1_pins_default {
  341. pinctrl-single,pins = <
  342. 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
  343. 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
  344. >;
  345. };
  346. };
  347. &uart0 {
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&uart0_pins>;
  350. status = "okay";
  351. };
  352. &uart1 {
  353. pinctrl-names = "default";
  354. pinctrl-0 = <&uart1_pins>;
  355. status = "okay";
  356. };
  357. &i2c0 {
  358. pinctrl-names = "default";
  359. pinctrl-0 = <&i2c0_pins>;
  360. status = "okay";
  361. clock-frequency = <400000>;
  362. tps: tps@24 {
  363. reg = <0x24>;
  364. };
  365. };
  366. &usb {
  367. status = "okay";
  368. };
  369. &usb_ctrl_mod {
  370. status = "okay";
  371. };
  372. &usb0_phy {
  373. status = "okay";
  374. };
  375. &usb1_phy {
  376. status = "okay";
  377. };
  378. &usb0 {
  379. status = "okay";
  380. };
  381. &usb1 {
  382. status = "okay";
  383. dr_mode = "host";
  384. };
  385. &cppi41dma {
  386. status = "okay";
  387. };
  388. &i2c1 {
  389. pinctrl-names = "default";
  390. pinctrl-0 = <&i2c1_pins>;
  391. status = "okay";
  392. clock-frequency = <100000>;
  393. lis331dlh: lis331dlh@18 {
  394. compatible = "st,lis331dlh", "st,lis3lv02d";
  395. reg = <0x18>;
  396. Vdd-supply = <&lis3_reg>;
  397. Vdd_IO-supply = <&lis3_reg>;
  398. st,click-single-x;
  399. st,click-single-y;
  400. st,click-single-z;
  401. st,click-thresh-x = <10>;
  402. st,click-thresh-y = <10>;
  403. st,click-thresh-z = <10>;
  404. st,irq1-click;
  405. st,irq2-click;
  406. st,wakeup-x-lo;
  407. st,wakeup-x-hi;
  408. st,wakeup-y-lo;
  409. st,wakeup-y-hi;
  410. st,wakeup-z-lo;
  411. st,wakeup-z-hi;
  412. st,min-limit-x = <120>;
  413. st,min-limit-y = <120>;
  414. st,min-limit-z = <140>;
  415. st,max-limit-x = <550>;
  416. st,max-limit-y = <550>;
  417. st,max-limit-z = <750>;
  418. };
  419. tsl2550: tsl2550@39 {
  420. compatible = "taos,tsl2550";
  421. reg = <0x39>;
  422. };
  423. tmp275: tmp275@48 {
  424. compatible = "ti,tmp275";
  425. reg = <0x48>;
  426. };
  427. tlv320aic3106: tlv320aic3106@1b {
  428. compatible = "ti,tlv320aic3106";
  429. reg = <0x1b>;
  430. status = "okay";
  431. /* Regulators */
  432. AVDD-supply = <&ldo2_reg>;
  433. IOVDD-supply = <&ldo2_reg>;
  434. DRVDD-supply = <&ldo2_reg>;
  435. DVDD-supply = <&vbat>;
  436. };
  437. };
  438. &lcdc {
  439. status = "okay";
  440. };
  441. &elm {
  442. status = "okay";
  443. };
  444. &epwmss0 {
  445. status = "okay";
  446. ecap0: ecap@48300100 {
  447. status = "okay";
  448. pinctrl-names = "default";
  449. pinctrl-0 = <&ecap0_pins>;
  450. };
  451. };
  452. &gpmc {
  453. status = "okay";
  454. pinctrl-names = "default";
  455. pinctrl-0 = <&nandflash_pins_s0>;
  456. /*ranges = <0 0 0x08000000 0x1000000>;*/ /* CS0: 16MB for NAND */
  457. ranges = <0 0 0x08000000 0x40000000>; /*+++ vern,NAND,20181030 ---*/
  458. nand@0,0 {
  459. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  460. ti,nand-ecc-opt = "bch16";
  461. ti,elm-id = <&elm>;
  462. nand-bus-width = <8>;
  463. gpmc,device-width = <1>;
  464. gpmc,sync-clk-ps = <0>;
  465. gpmc,cs-on-ns = <0>;
  466. gpmc,cs-rd-off-ns = <44>;
  467. gpmc,cs-wr-off-ns = <44>;
  468. gpmc,adv-on-ns = <6>;
  469. gpmc,adv-rd-off-ns = <34>;
  470. gpmc,adv-wr-off-ns = <44>;
  471. gpmc,we-on-ns = <0>;
  472. gpmc,we-off-ns = <40>;
  473. gpmc,oe-on-ns = <0>;
  474. gpmc,oe-off-ns = <54>;
  475. gpmc,access-ns = <64>;
  476. gpmc,rd-cycle-ns = <82>;
  477. gpmc,wr-cycle-ns = <82>;
  478. gpmc,wait-on-read = "true";
  479. gpmc,wait-on-write = "true";
  480. gpmc,bus-turnaround-ns = <0>;
  481. gpmc,cycle2cycle-delay-ns = <0>;
  482. gpmc,clk-activation-ns = <0>;
  483. gpmc,wait-monitoring-ns = <0>;
  484. gpmc,wr-access-ns = <40>;
  485. gpmc,wr-data-mux-bus-ns = <0>;
  486. /* MTD partition table */
  487. /* All SPL-* partitions are sized to minimal length
  488. * which can be independently programmable. For
  489. * NAND flash this is equal to size of erase-block */
  490. #address-cells = <1>;
  491. #size-cells = <1>;
  492. partition@0 {
  493. label = "SPL";
  494. reg = <0x00000000 0x00080000>;
  495. };
  496. partition@1 {
  497. label = "Primary u-boot";
  498. reg = <0x00080000 0x00100000>;
  499. };
  500. partition@2 {
  501. label = "u-boot-env";
  502. reg = <0x00180000 0x00080000>;
  503. };
  504. partition@3 {
  505. label = "Secondary u-boot";
  506. reg = <0x00200000 0x00100000>;
  507. };
  508. partition@4 {
  509. label = "Primary dtb";
  510. reg = <0x00300000 0x00080000>;
  511. };
  512. partition@5 {
  513. label = "Secondary dtb";
  514. reg = <0x00380000 0x00080000>;
  515. };
  516. partition@6 {
  517. label = "Primary kernel";
  518. reg = <0x00400000 0x00A00000>;
  519. };
  520. partition@7 {
  521. label = "Secondary kernel";
  522. reg = <0x00E00000 0x00A00000>;
  523. };
  524. partition@8 {
  525. label = "Primary rootfs";
  526. reg = <0x03000000 0x03000000>;
  527. };
  528. partition@9 {
  529. label = "Secondary rootfs";
  530. reg = <0x06000000 0x03000000>;
  531. };
  532. partition@10 {
  533. label = "Primary user configuration";
  534. reg = <0x09000000 0x00600000>;
  535. };
  536. partition@11 {
  537. label = "Secondary user configuration";
  538. reg = <0x09600000 0x00600000>;
  539. };
  540. partition@12 {
  541. label = "Factory default configuration";
  542. reg = <0x09C00000 0x00600000>;
  543. };
  544. partition@13 {
  545. label = "Storage";
  546. reg = <0x0A200000 0x35E00000>;
  547. };
  548. };
  549. };
  550. /include/ "tps65217.dtsi"
  551. &tps {
  552. /*
  553. * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
  554. * mode") at poweroff. Most BeagleBone versions do not support RTC-only
  555. * mode and risk hardware damage if this mode is entered.
  556. *
  557. * For details, see linux-omap mailing list May 2015 thread
  558. * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
  559. * In particular, messages:
  560. * http://www.spinics.net/lists/linux-omap/msg118585.html
  561. * http://www.spinics.net/lists/linux-omap/msg118615.html
  562. *
  563. * You can override this later with
  564. * &tps { /delete-property/ ti,pmic-shutdown-controller; }
  565. * if you want to use RTC-only mode and made sure you are not affected
  566. * by the hardware problems. (Tip: double-check by performing a current
  567. * measurement after shutdown: it should be less than 1 mA.)
  568. */
  569. ti,pmic-shutdown-controller;
  570. regulators {
  571. dcdc1_reg: regulator@0 {
  572. regulator-name = "vdds_dpr";
  573. regulator-always-on;
  574. };
  575. dcdc2_reg: regulator@1 {
  576. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  577. regulator-name = "vdd_mpu";
  578. regulator-min-microvolt = <1100000>;
  579. regulator-max-microvolt = <1325000>;
  580. regulator-boot-on;
  581. regulator-always-on;
  582. };
  583. dcdc3_reg: regulator@2 {
  584. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  585. regulator-name = "vdd_core";
  586. regulator-min-microvolt = <925000>;
  587. regulator-max-microvolt = <1150000>;
  588. regulator-boot-on;
  589. regulator-always-on;
  590. };
  591. ldo1_reg: regulator@3 {
  592. regulator-name = "vio,vrtc,vdds";
  593. regulator-always-on;
  594. };
  595. ldo2_reg: regulator@4 {
  596. regulator-name = "vdd_3v3aux";
  597. regulator-always-on;
  598. };
  599. ldo3_reg: regulator@5 {
  600. regulator-name = "vdd_1v8";
  601. regulator-always-on;
  602. };
  603. ldo4_reg: regulator@6 {
  604. regulator-name = "vdd_3v3a";
  605. regulator-always-on;
  606. };
  607. };
  608. };
  609. &mac {
  610. pinctrl-names = "default", "sleep";
  611. pinctrl-0 = <&cpsw_default>;
  612. pinctrl-1 = <&cpsw_sleep>;
  613. status = "okay";
  614. };
  615. &davinci_mdio {
  616. pinctrl-names = "default", "sleep";
  617. pinctrl-0 = <&davinci_mdio_default>;
  618. pinctrl-1 = <&davinci_mdio_sleep>;
  619. status = "okay";
  620. };
  621. &cpsw_emac0 {
  622. phy_id = <&davinci_mdio>, <1>;
  623. phy-mode = "mii";
  624. };
  625. &cpsw_emac1 {
  626. phy_id = <&davinci_mdio>, <2>;
  627. phy-mode = "mii";
  628. };
  629. &tscadc {
  630. status = "okay";
  631. tsc {
  632. ti,wires = <4>;
  633. ti,x-plate-resistance = <200>;
  634. ti,coordinate-readouts = <5>;
  635. ti,wire-config = <0x00 0x11 0x22 0x33>;
  636. ti,charge-delay = <0x400>;
  637. };
  638. adc {
  639. ti,adc-channels = <4 5 6 7>;
  640. };
  641. };
  642. &mmc1 {
  643. status = "okay";
  644. vmmc-supply = <&ldo4_reg>;
  645. bus-width = <4>;
  646. pinctrl-names = "default";
  647. pinctrl-0 = <&mmc1_pins_default>;
  648. cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  649. };
  650. &mmc3 {
  651. /* these are on the crossbar and are outlined in the
  652. xbar-event-map element */
  653. dmas = <&edma 12
  654. &edma 13>;
  655. dma-names = "tx", "rx";
  656. status = "okay";
  657. vmmc-supply = <&wlan_en_reg>;
  658. bus-width = <4>;
  659. pinctrl-names = "default";
  660. pinctrl-0 = <&mmc3_pins &wlan_pins>;
  661. ti,non-removable;
  662. ti,needs-special-hs-handling;
  663. cap-power-off-card;
  664. keep-power-in-suspend;
  665. #address-cells = <1>;
  666. #size-cells = <0>;
  667. wlcore: wlcore@0 {
  668. compatible = "ti,wl1835";
  669. reg = <2>;
  670. interrupt-parent = <&gpio3>;
  671. interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
  672. };
  673. };
  674. &edma {
  675. ti,edma-xbar-event-map = /bits/ 16 <1 12
  676. 2 13>;
  677. };
  678. &sham {
  679. status = "okay";
  680. };
  681. &aes {
  682. status = "okay";
  683. };
  684. &dcan1 {
  685. status = "disabled"; /* Enable only if Profile 1 is selected */
  686. pinctrl-names = "default";
  687. pinctrl-0 = <&dcan1_pins_default>;
  688. };